1. Field of the Invention
The present invention relates to a voltage window detector and in particular to an integrated circuit CMOS window detector having an output exhibiting hysteresis.
2. Description of the Prior Art
A voltage window detector is a commonly used circuit element which provides outputs indicating whether an input voltage is within a "window" defined by a high and a low voltage level. The prior art includes several window detector circuits suitable for use in an integrated circuit. Nutz Pat. No. 4,184,087, Tanaka Pat. No. 4,292,552 and Dunphy et al Pat. No. 4,300,063 all describe window detectors using bipolar transistors. These circuits are implemented using many elements, and are not described as being insensitive to semiconductor process variations. All of these designs establish the threshold level of the window by means of a resistive voltage divider network.
The Dingwall Pat. No. 4,262,221 is an FET voltage comparator circuit designed for integration on a silicon-on-sapphire monolithic die. A technique for minimizing the transient offsets associated with this type of technology is described. The Musa et al Pat. No. 4,224,539 describes a FET voltage level detector which is insensitive to variations in power supply voltage.
There is a continuing need for improved integrated circuit voltage window detectors which utilize fewer components than the prior art, thus reducing area used on the integrated circuit chip and improving reliability. In addition, an integrated circuit window detector with reduced power consumption, insensitivity to semiconductor process variations, reduced temperature sensitivity, higher speed, and capability of operating with low supply voltages is needed.